/* * William L. Bahn */ module DE248 ( D2_OSC, D2_BTN, D2_LED, // On-board I/O D2_TXD, D2_RXD, D2_RTS, D2_CTS, D2_DSR, // RS232 Interface PortA, PortB, PortC, PortD, // Expansion Ports ); input D2_OSC, D2_BTN; // On-board I/O output D2_LED; // " input D2_TXD, D2_RTS; // RS232 INTERFACE output D2_RXD, D2_CTS, D2_DSR; // " inout [40:4] PortA; // 37-bit I/O port inout [12:4] PortB; // 9-bit I/O port inout [40:4] PortC; // 37-bit I/O port inout [40:4] PortD; // 37-bit I/O port parameter LO = 1'b0, HI = 1'b1; parameter REGWIDTH = 8; wire rst, clk; // ====================================================================== // Dual Port RAM (Inferred BlockRAM) // ====================================================================== wire [15:0] DPRAM_WA; wire [63:0] DPRAM_WD; wire DPRAM_WE; wire [15:0] DPRAM_RA; wire [63:0] DPRAM_RD; wire [ 7:0] DPRAM_CTL; assign DPRAM_WE = DPRAM_CTL[0]; DualPortBlockRAM512x64 DPRAM ( .WriteAddress(DPRAM_WA[8:0]), .DataIn(DPRAM_WD), .WriteEnable(DPRAM_WE), .ReadAddress(DPRAM_RA[8:0]), .DataOut(DPRAM_RD), .clk(clk) ); // ====================================================================== // Loop Controller // ====================================================================== wire [ 7:0] LOOP_CR; wire [15:0] LOOP_CRD; wire [ 7:0] LOOP_Test; wire [15:0] LOOP_Time; wire [15:0] LOOP_IP; wire LOOP_IP_Load; LoopController LOOP_CTLR ( .Test(LOOP_Test), .Time(LOOP_Time), .CR(LOOP_CR), .Data(LOOP_CRD), .IP(LOOP_IP), .IP_Load(LOOP_IP_Load), .rst(rst), .clk(clk) ); // ====================================================================== // Instruction Fetch Module // ====================================================================== wire [15:0] INST_Pointer; wire [ 2:0] INST_Length; wire INST_Fetch; wire [63:0] INST_Instruction; wire INST_DataValid; // Read Pipe Signals wire [23:0] INST_RP_DataIn, INST_RP_DataOut; wire INST_RP_Push, INST_RP_Pop; wire INST_RP_FF, INST_RP_AF, INST_RP_EF; // Readback Pipe Signals wire [31:0] INST_RB_DataIn, INST_RB_DataOut; wire INST_RB_Push, INST_RB_Pop; wire INST_RB_FF, INST_RB_AF, INST_RB_EF; wire [ 7:0] INST_Test; /* // FPGA BlockRAM Signals wire [ 7:0] BLK_Test; wire [ 7:0] BLK_Pointer; wire [63:0] BLK_Data; wire BLK_ReadRequest; wire BLK_DataStrobe; FPGA_BlockRAM BLKRAM ( .Test(BLK_Test), .ReadPointer(BLK_Pointer), .ReadData(BLK_Data), .ReadRequest(BLK_ReadRequest), .ReadDataStrobe(BLK_DataStrobe), .rst(rst), .clk(clk) ); */ INSTRUCTION_FETCH IF ( .Test(INST_Test), // SPI Processor Interface .Pointer(INST_Pointer), .Fetch(INST_Fetch), .Instruction(INST_Instruction), .DataValid(INST_DataValid), // FPGA BlockRAM Interface .DPRAM_RA(DPRAM_RA), .DPRAM_RD(DPRAM_RD), // Global Reset and Clock .rst(rst), .clk(clk) ); /* INSTRUCTION_FETCH_A IF ( .Test(INST_Test), // SPI Processor Interface .Pointer(INST_Pointer), .Fetch(INST_Fetch), .Instruction(INST_Instruction), .DataValid(INST_DataValid), // FPGA BlockRAM Interface .BLK_Pointer(BLK_Pointer), .BLK_Data(BLK_Data), .BLK_ReadRequest(BLK_ReadRequest), .BLK_DataStrobe(BLK_DataStrobe), // Global Reset and Clock .rst(rst), .clk(clk) ); */ // ====================================================================== // SPI INTERFACE // ====================================================================== // SPI_HOST_Source: 0x10 = Loop Controller; 0x01 = Execute (HOST) // Signals: from HOST from LOOP to SPI wire [7:0] SPI_HOST_Source; wire [15:0] SPI_HOST_Packet_TX, SPI_LOOP_Packet_TX, SPI_Packet_TX; wire [7:0] SPI_HOST_Length, SPI_LOOP_Length, SPI_Length; wire [7:0] SPI_HOST_ClkDiv, SPI_ClkDiv; wire [7:0] SPI_HOST_Target, SPI_LOOP_Target, SPI_Target; wire [7:0] SPI_HOST_Control, SPI_Control; wire SPI_HOST_Initiate, SPI_LOOP_Initiate, SPI_Initiate; // Signals: to HOST to LOOP from SPI wire [15:0] SPI_Packet_RX; wire SPI_Busy; // Parsed/Derived Signals wire SPI_Loop_Select; assign SPI_Loop_Select = SPI_HOST_Source[4]; assign SPI_HOST_Initiate = SPI_HOST_Source[0]; assign SPI_ClkDiv = SPI_HOST_ClkDiv; assign SPI_Control = SPI_HOST_Control; // ====================================================================== // SPI Processor // ====================================================================== wire [ 7:0] SPI_PROC_Test; SPI_PROCESSOR SPIPROC ( .Test(SPI_PROC_Test), // Loop Controller Interface .Time(LOOP_Time), .IP(LOOP_IP), .IP_Load(LOOP_IP_Load), // Instruction Memory Interface .Pointer(INST_Pointer), .Fetch(INST_Fetch), .Instruction(INST_Instruction), .DataValid(INST_DataValid), // SPI Interface .Packet(SPI_LOOP_Packet_TX), .PacketLength(SPI_LOOP_Length), .Target(SPI_LOOP_Target), .Initiate(SPI_LOOP_Initiate), .Busy(SPI_Busy), // Global Clock/Reset .rst(rst), .clk(clk) ); // ====================================================================== // SPI Entry MUX // ====================================================================== MUX2 SPIMUX_INITIATE ( .Q(SPI_Initiate), .D1(SPI_LOOP_Initiate), .D0(SPI_HOST_Initiate), .Sel(SPI_Loop_Select) ); MUX2x8 SPIMUX_TARGET ( .Q(SPI_Target), .D1(SPI_LOOP_Target), .D0(SPI_HOST_Target), .Sel(SPI_Loop_Select) ); MUX2x8 SPIMUX_LENGTH ( .Q(SPI_Length), .D1(SPI_LOOP_Length), .D0(SPI_HOST_Length), .Sel(SPI_Loop_Select) ); MUX2x16 SPIMUX_PACKET ( .Q(SPI_Packet_TX), .D1(SPI_LOOP_Packet_TX), .D0(SPI_HOST_Packet_TX), .Sel(SPI_Loop_Select) ); // ====================================================================== // SPI MASTER // ====================================================================== // SPI Control Map // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | // |MISO_INV|MOSI_INV| SSN_INV| SCK_INV|FreeRun | Dir | CPOL | CPHA | // External Interface wire SCK, MOSI, MISO; wire [7:0] SSN; // Test Signal Interface wire [15:0] SPI_Test; SPI_MASTER_phy SPI_PHY ( .Test8(SPI_Test[7:0]), .packet_RX(SPI_Packet_RX), .packet_TX(SPI_Packet_TX), .initiate(SPI_Initiate), .length(SPI_Length), .control(SPI_Control), .clkdiv(SPI_ClkDiv), .target(SPI_Target), .busy(SPI_Busy), .MOSI(MOSI), .MISO(MISO), .SCK(SCK), .SSN(SSN), .rst(rst), .clk(clk) ); assign SPI_Test[15] = SPI_Busy; assign SPI_Test[14] = SPI_HOST_Source[0]; assign SPI_Test[13] = SPI_Packet_TX[0]; assign SPI_Test[12] = SPI_Initiate; assign SPI_Test[11] = MISO; assign SPI_Test[10] = MOSI; assign SPI_Test[9] = SSN[0]; assign SPI_Test[8] = SCK; // ====================================================================== // Memory Module Interface // ====================================================================== // Test Interface wire [7:0] SRAM_Test; wire [7:0] PIPE_Test; wire [7:0] SRAM_Control; wire [23:0] SRAM_Ain; wire [23:0] SRAM_Aout; wire [7:0] SRAM_WD; wire [7:0] SRAM_Status; wire [7:0] SRAM_RD; wire [31:0] HOST_WP_DataOut, HOST_WP_DataIn; wire HOST_WP_Push, HOST_WP_Pop; wire HOST_WP_FF, HOST_WP_EF, HOST_WP_AF; wire [23:0] HOST_RP_DataOut, HOST_RP_DataIn; wire HOST_RP_Push, HOST_RP_Pop; wire HOST_RP_FF, HOST_RP_EF, HOST_RP_AF; wire [31:0] HOST_RB_DataOut, HOST_RB_DataIn; wire HOST_RB_Push, HOST_RB_Pop; wire HOST_RB_FF, HOST_RB_EF, HOST_RB_AF; wire [31:0] WP_DataOut; wire [23:0] RP_DataOut; wire [31:0] RB_DataIn; wire WP_Push, WP_Pop, WP_FF, WP_EF, WP_AF; wire RP_Push, RP_Pop, RP_FF, RP_EF, RP_AF; wire RB_Push, RB_Pop, RB_FF, RB_EF, RB_AF; SRAM_REG_IO SRAM_REG ( .Test8(SRAM_Test), .Control(SRAM_Control), // Control Register .Ain(SRAM_Ain), // Input Addr .WD(SRAM_WD), // Write Data .Status(SRAM_Status), // Status Register .RD(SRAM_RD), // Read Data .Aout(SRAM_Aout), // Output Addr .WP_DataIn(HOST_WP_DataIn), .WP_Push(HOST_WP_Push), .WP_FF(HOST_WP_FF), .RP_DataIn(HOST_RP_DataIn), .RP_Push(HOST_RP_Push), .RP_FF(HOST_RP_FF), .RB_DataOut(HOST_RB_DataOut), .RB_Pop(HOST_RB_Pop), .RB_EF(HOST_RB_EF), .rst(rst), .clk(clk) ); // ====================================================================== // VGA Display Driver // ====================================================================== // Read Pipe Signals wire [23:0] DISP_RP_DataIn, DISP_RP_DataOut; wire DISP_RP_Push, DISP_RP_Pop; wire DISP_RP_FF, DISP_RP_AF, DISP_RP_EF; // Readback Pipe Signals wire [31:0] DISP_RB_DataOut, DISP_RB_DataIn; wire DISP_RB_Push, DISP_RB_Pop; wire DISP_RB_FF, DISP_RB_AF, DISP_RB_EF; // ====================================================================== // CHIP Data // ====================================================================== // Write Pipe Signals wire [31:0] CHIP_WP_DataIn, CHIP_WP_DataOut; wire CHIP_WP_Push, CHIP_WP_Pop; wire CHIP_WP_FF, CHIP_WP_AF, CHIP_WP_EF; // ====================================================================== // SRAM Write Pipes // ====================================================================== wire [7:0] Test_WPMUX, Test_RPMUX, Test_RBMUX; FIFO16x32 HOST_WRITE_PIPE ( .DataOut(HOST_WP_DataOut), .DataIn(HOST_WP_DataIn), .Push(HOST_WP_Push), .FF(HOST_WP_FF), .AF(HOST_WP_AF), .Pop(HOST_WP_Pop), .EF(HOST_WP_EF), .Dump(rst), .Clk(clk) ); FIFO16x32 CHIP_WRITE_PIPE ( .DataOut(CHIP_WP_DataOut), .DataIn(CHIP_WP_DataIn), .Push(CHIP_WP_Push), .FF(CHIP_WP_FF), .AF(CHIP_WP_AF), .Pop(CHIP_WP_Pop), .EF(CHIP_WP_EF), .Dump(rst), .Clk(clk) ); WRITE_PIPE_MUX WP_MUX ( .Test(Test_WPMUX), .Pipe0_DataOut(HOST_WP_DataOut), .Pipe0_Pop(HOST_WP_Pop), .Pipe0_FF(HOST_WP_FF), .Pipe0_AF(HOST_WP_AF), .Pipe0_EF(HOST_WP_EF), .Pipe1_DataOut(CHIP_WP_DataOut), .Pipe1_Pop(CHIP_WP_Pop), .Pipe1_FF(CHIP_WP_FF), .Pipe1_AF(CHIP_WP_AF), .Pipe1_EF(CHIP_WP_EF), // Write Pipe .WP_Data(WP_DataOut), .WP_Pop(WP_Pop), .WP_EF(WP_EF), .WP_AF(WP_AF), // Global Reset and Clock .rst(rst), .clk(clk) ); // ====================================================================== // SRAM Read Pipes // ====================================================================== FIFO16x24 HOST_READ_PIPE ( .DataOut(HOST_RP_DataOut), .DataIn(HOST_RP_DataIn), .Push(HOST_RP_Push), .FF(HOST_RP_FF), .AF(HOST_RP_AF), .Pop(HOST_RP_Pop), .EF(HOST_RP_EF), .Dump(rst), .Clk(clk) ); FIFO16x24 INST_READ_PIPE ( .DataOut(INST_RP_DataOut), .DataIn(INST_RP_DataIn), .Push(INST_RP_Push), .FF(INST_RP_FF), .AF(INST_RP_AF), .Pop(INST_RP_Pop), .EF(INST_RP_EF), .Dump(rst), .Clk(clk) ); FIFO16x24 DISP_READ_PIPE ( .DataOut(DISP_RP_DataOut), .DataIn(DISP_RP_DataIn), .Push(DISP_RP_Push), .FF(DISP_RP_FF), .AF(DISP_RP_AF), .Pop(DISP_RP_Pop), .EF(DISP_RP_EF), .Dump(rst), .Clk(clk) ); READ_PIPE_MUX RP_MUX ( .Test(Test_RPMUX), .Pipe0_DataOut(HOST_RP_DataOut), .Pipe0_Pop(HOST_RP_Pop), .Pipe0_FF(HOST_RP_FF), .Pipe0_AF(HOST_RP_AF), .Pipe0_EF(HOST_RP_EF), .Pipe1_DataOut(INST_RP_DataOut), .Pipe1_Pop(INST_RP_Pop), .Pipe1_FF(INST_RP_FF), .Pipe1_AF(INST_RP_AF), .Pipe1_EF(INST_RP_EF), .Pipe2_DataOut(DISP_RP_DataOut), .Pipe2_Pop(DISP_RP_Pop), .Pipe2_FF(DISP_RP_FF), .Pipe2_AF(DISP_RP_AF), .Pipe2_EF(DISP_RP_EF), // Read Request Pipe .RP_Data(RP_DataOut), .RP_Pop(RP_Pop), .RP_EF(RP_EF), .RP_AF(RP_AF), // Global Reset and Clock .rst(rst), .clk(clk) ); // ====================================================================== // SRAM Readback Pipes // ====================================================================== FIFO16x32 HOST_READBACK_PIPE ( .DataOut(HOST_RB_DataOut), .DataIn(HOST_RB_DataIn), .Push(HOST_RB_Push), .FF(HOST_RB_FF), .Pop(HOST_RB_Pop), .EF(HOST_RB_EF), .Dump(rst), .Clk(clk) ); FIFO16x32 INST_READBACK_PIPE ( .DataOut(INST_RB_DataOut), .DataIn(INST_RB_DataIn), .Push(INST_RB_Push), .FF(INST_RB_FF), .Pop(INST_RB_Pop), .EF(INST_RB_EF), .Dump(rst), .Clk(clk) ); FIFO16x32 DISP_READBACK_PIPE ( .DataOut(DISP_RB_DataOut), .DataIn(DISP_RB_DataIn), .Push(DISP_RB_Push), .FF(DISP_RB_FF), .Pop(DISP_RB_Pop), .EF(DISP_RB_EF), .Dump(rst), .Clk(clk) ); READBACK_PIPE_MUX RB_MUX ( .Test(Test_RBMUX), .Pipe0_DataIn(HOST_RB_DataIn), .Pipe0_Push(HOST_RB_Push), .Pipe0_FF(HOST_RB_FF), .Pipe0_EF(HOST_RB_EF), .Pipe1_DataIn(INST_RB_DataIn), .Pipe1_Push(INST_RB_Push), .Pipe1_FF(INST_RB_FF), .Pipe1_EF(INST_RB_EF), .Pipe2_DataIn(DISP_RB_DataIn), .Pipe2_Push(DISP_RB_Push), .Pipe2_FF(DISP_RB_FF), .Pipe2_EF(DISP_RB_EF), // Readback Pipe .RB_Data(RB_DataIn), .RB_Push(RB_Push), .RB_FF(RB_FF), // Global Reset and Clock .rst(rst), .clk(clk) ); // ====================================================================== // SRAM I/O Pipe Switches // ====================================================================== // External Interface wire [18:0] MEM1_A; wire [7:0] MEM1_WD; // Write to the MEM1 Board wire [7:0] MEM1_RD; // Read from the MEM1 Board wire [1:0] MEM1_CS; wire MEM1_OEb; wire MEM1_WEb; SRAM_PipeManager PIPE_MNGR ( // Test Port .Test8(PIPE_Test), // Write Pipe .WP_Data(WP_DataOut), .WP_Pop(WP_Pop), .WP_EF(WP_EF), .WP_AF(WP_AF), // Read Request Pipe .RP_Data(RP_DataOut), .RP_Pop(RP_Pop), .RP_EF(RP_EF), .RP_AF(RP_AF), // Readback Pipe .RB_Data(RB_DataIn), .RB_Push(RB_Push), .RB_FF(RB_FF), // Memory Module Interface .A(MEM1_A), .CSb(MEM1_CS), .OEb(MEM1_OEb), .WEb(MEM1_WEb), .DI(MEM1_WD), .DO(MEM1_RD), // Global Reset and Clock .rst(rst), .clk(clk) ); // ====================================================================== // Pulse Generator Bank // ====================================================================== wire [7:0] PulseEn; wire [7:0] PulseRstB; wire [7:0] Pulse; wire [7:0] PeriodByte0, PeriodByte1, PeriodByte2, PeriodByte3; wire [7:0] PeriodByte4, PeriodByte5, PeriodByte6, PeriodByte7; wire [7:0] PeriodByte8, PeriodByte9, PeriodByteA, PeriodByteB; wire [7:0] PeriodByteC, PeriodByteD, PeriodByteE, PeriodByteF; wire [ 7:0] Period1, Period0; wire [15:0] Period5, Period4, Period3, Period2; wire [23:0] Period7, Period6; assign Period0 = {PeriodByte0}; assign Period1 = {PeriodByte1}; assign Period2 = {PeriodByte3,PeriodByte2}; assign Period3 = {PeriodByte5,PeriodByte4}; assign Period4 = {PeriodByte7,PeriodByte6}; assign Period5 = {PeriodByte9,PeriodByte8}; assign Period6 = {PeriodByteC,PeriodByteB,PeriodByteA}; assign Period7 = {PeriodByteF,PeriodByteE,PeriodByteD}; PulseGen8 PULSE0 (.Q(Pulse[0]), .Period(Period0), .en(PulseEn[0]), .rst(~PulseRstB[0]), .clk(clk)); PulseGen8 PULSE1 (.Q(Pulse[1]), .Period(Period1), .en(PulseEn[1]), .rst(~PulseRstB[1]), .clk(clk)); PulseGen16 PULSE2 (.Q(Pulse[2]), .Period(Period2), .en(PulseEn[2]), .rst(~PulseRstB[2]), .clk(clk)); PulseGen16 PULSE3 (.Q(Pulse[3]), .Period(Period3), .en(PulseEn[3]), .rst(~PulseRstB[3]), .clk(clk)); PulseGen16 PULSE4 (.Q(Pulse[4]), .Period(Period4), .en(PulseEn[4]), .rst(~PulseRstB[4]), .clk(clk)); PulseGen16 PULSE5 (.Q(Pulse[5]), .Period(Period5), .en(PulseEn[5]), .rst(~PulseRstB[5]), .clk(clk)); PulseGen24 PULSE6 (.Q(Pulse[6]), .Period(Period6), .en(PulseEn[6]), .rst(~PulseRstB[6]), .clk(clk)); PulseGen24 PULSE7 (.Q(Pulse[7]), .Period(Period7), .en(PulseEn[7]), .rst(~PulseRstB[7]), .clk(clk)); // ====================================================================== // Square Wave Generator Bank // ====================================================================== wire [7:0] SquareEn; wire [7:0] SquareRstB; wire [7:0] Square; wire [7:0] SqEn; assign SqEn = (Pulse & SquareEn); DFFRen SQ0 (.Q(Square[0]), .D(~Square[0]), .en(SqEn[0]), .rst(~SquareRstB[0]), .clk(clk)); DFFRen SQ1 (.Q(Square[1]), .D(~Square[1]), .en(SqEn[1]), .rst(~SquareRstB[1]), .clk(clk)); DFFRen SQ2 (.Q(Square[2]), .D(~Square[2]), .en(SqEn[2]), .rst(~SquareRstB[2]), .clk(clk)); DFFRen SQ3 (.Q(Square[3]), .D(~Square[3]), .en(SqEn[3]), .rst(~SquareRstB[3]), .clk(clk)); DFFRen SQ4 (.Q(Square[4]), .D(~Square[4]), .en(SqEn[4]), .rst(~SquareRstB[4]), .clk(clk)); DFFRen SQ5 (.Q(Square[5]), .D(~Square[5]), .en(SqEn[5]), .rst(~SquareRstB[5]), .clk(clk)); DFFRen SQ6 (.Q(Square[6]), .D(~Square[6]), .en(SqEn[6]), .rst(~SquareRstB[6]), .clk(clk)); DFFRen SQ7 (.Q(Square[7]), .D(~Square[7]), .en(SqEn[7]), .rst(~SquareRstB[7]), .clk(clk)); // ====================================================================== // Gray Code CODEC // ====================================================================== wire [11:0] Binary; wire [11:0] Gray; wire [11:0] RecoveredBinary; wire GrayMarker; assign GrayMarker = Binary[11]; Counter12 BC (.Q(Binary), .en(Pulse[7]), .rst(rst), .clk(clk)); Binary2Gray12 B2G ( .Gray(Gray), .Binary(Binary), .rst(rst), .clk(clk)); Gray2Binary12 G2B ( .Binary(RecoveredBinary), .Gray(Gray), .rst(rst), .clk(clk)); // ====================================================================== // RS-232 UART to REGISTER MODULE // ====================================================================== // External Interface Signals wire TXD, RXD, RTS, CTS, DSR; // Internal Interface Signals wire [7:0] UART_Control; wire RS232_Escape, RS232_DataLost; // Address and Data Registers (byte-wide) wire [(REGWIDTH-1):0] regRA, regWA; wire [(REGWIDTH-1):0] regWD, regRD; wire regWS; wire [7:0] REG_TestH, REG_TestL; wire [7:0] UART_TestH, UART_TestL; RS232toMEM UART ( .Test16({UART_TestH,UART_TestL}), .Test({REG_TestH,REG_TestL}), .WA(regWA), .WD(regWD), .RA(regRA), .DataIn(regRD), .WS(regWS), .NoEcho(UART_Control[0]), .NoXonXoff(UART_Control[4]), .Escape(RS232_Escape), .Lost(RS232_DataLost), .TXD(TXD), .RXD(RXD), .RTS(RTS), .CTS(CTS), .DSR(DSR), .rst(rst), .clk(clk) ); // ====================================================================== // Test Port Interface // ====================================================================== // External Interface wire [15:0] Test; // Internal Interface wire [7:0] TestSel; MUX16x8 TestMuxH ( .Q(Test[15:8]), .DF({SRAM_Test[3:0],PIPE_Test[3:0]}), .DE({GrayMarker, 3'b000, RecoveredBinary[11:8]}), .DD(MEM1_DO), .DC(SPI_TestH), .DB(SPI_TestL), .DA(Pulse), .D9(Square), .D8(RecoveredBinary[7:0]), .D7(DPRAM_RD[7:0]), //{GrayMarker, 3'b000, Gray[11:8]}), .D6(INST_Instruction[63:56]), //Gray[7:0]), .D5(SPI_IF_Test), .D4(SPI_PROC_Test), .D3(DPRAM_RA[7:0]), // ({GrayMarker, 3'b000, Binary[11:8]}), .D2(INST_Instruction[7:0]), // (Binary[7:0]), .D1(Test_WPMUX), .D0(Test_RBMUX), .Sel(TestSel[7:4]) ); MUX16x8 TestMuxL ( .Q(Test[7:0]), .DF(REG_TestH), .DE(REG_TestL), .DD(SRAM_Test), .DC(SRAM_Test), .DB({PIPE_Test[7:4],MEM1_CS,MEM1_OE,MEM1_WE}), .DA(LOOP_Time[7:0]), .D9(8'hFF),//DPRAM[7:0]),//BLK_Test), .D8(UART_TestL), .D7({GrayMarker, 3'b000, RecoveredBinary[11:8]}), .D6(LOOP_Test), .D5(LOOP_IP[15:8]), .D4(LOOP_IP[7:0]), .D3(LOOP_Time[15:8]), .D2(LOOP_Time[7:0]), .D1(PIPE_Test), .D0(Test_RPMUX),//,UART_TestH), .Sel(TestSel[3:0]) ); // ====================================================================== // GENERAL PURPOSE I/O SIGNALS // ====================================================================== wire [23:0] I, O, OE; // ====================================================================== // GLOBAL HOST/FPGA REGISTER SPACE // ====================================================================== // HOST register outputs wire [7:0] HR00, HR01, HR02, HR03, HR04, HR05, HR06, HR07; wire [7:0] HR08, HR09, HR0A, HR0B, HR0C, HR0D, HR0E, HR0F; wire [7:0] HR10, HR11, HR12, HR13, HR14, HR15, HR16, HR17; wire [7:0] HR18, HR19, HR1A, HR1B, HR1C, HR1D, HR1E, HR1F; wire [7:0] HR20, HR21, HR22, HR23, HR24, HR25, HR26, HR27; wire [7:0] HR28, HR29, HR2A, HR2B, HR2C, HR2D, HR2E, HR2F; wire [7:0] HR30, HR31, HR32, HR33, HR34, HR35, HR36, HR37; wire [7:0] HR38, HR39, HR3A, HR3B, HR3C, HR3D, HR3E, HR3F; // FPGA register inputs wire [7:0] FR80, FR81, FR82, FR83, FR84, FR85, FR86, FR87; wire [7:0] FR88, FR89, FR8A, FR8B, FR8C, FR8D, FR8E, FR8F; wire [7:0] FR90, FR91, FR92, FR93, FR94, FR95, FR96, FR97; wire [7:0] FR98, FR99, FR9A, FR9B, FR9C, FR9D, FR9E, FR9F; wire [7:0] FRA0, FRA1, FRA2, FRA3, FRA4, FRA5, FRA6, FRA7; wire [7:0] FRA8, FRA9, FRAA, FRAB, FRAC, FRAD, FRAE, FRAF; wire [7:0] FRB0, FRB1, FRB2, FRB3, FRB4, FRB5, FRB6, FRB7; wire [7:0] FRB8, FRB9, FRBA, FRBB, FRBC, FRBD, FRBE, FRBF; RegSpace REGS ( // HOST register outputs .HR00(HR00), .HR01(HR01), .HR02(HR02), .HR03(HR03), .HR04(HR04), .HR05(HR05), .HR06(HR06), .HR07(HR07), .HR08(HR08), .HR09(HR09), .HR0A(HR0A), .HR0B(HR0B), .HR0C(HR0C), .HR0D(HR0D), .HR0E(HR0E), .HR0F(HR0F), .HR10(HR10), .HR11(HR11), .HR12(HR12), .HR13(HR13), .HR14(HR14), .HR15(HR15), .HR16(HR16), .HR17(HR17), .HR18(HR18), .HR19(HR19), .HR1A(HR1A), .HR1B(HR1B), .HR1C(HR1C), .HR1D(HR1D), .HR1E(HR1E), .HR1F(HR1F), .HR20(HR20), .HR21(HR21), .HR22(HR22), .HR23(HR23), .HR24(HR24), .HR25(HR25), .HR26(HR26), .HR27(HR27), .HR28(HR28), .HR29(HR29), .HR2A(HR2A), .HR2B(HR2B), .HR2C(HR2C), .HR2D(HR2D), .HR2E(HR2E), .HR2F(HR2F), .HR30(HR30), .HR31(HR31), .HR32(HR32), .HR33(HR33), .HR34(HR34), .HR35(HR35), .HR36(HR36), .HR37(HR37), .HR38(HR38), .HR39(HR39), .HR3A(HR3A), .HR3B(HR3B), .HR3C(HR3C), .HR3D(HR3D), .HR3E(HR3E), .HR3F(HR3F), // FPGA register inputs .FR00(FR80), .FR01(FR81), .FR02(FR82), .FR03(FR83), .FR04(FR84), .FR05(FR85), .FR06(FR86), .FR07(FR87), .FR08(FR88), .FR09(FR89), .FR0A(FR8A), .FR0B(FR8B), .FR0C(FR8C), .FR0D(FR8D), .FR0E(FR8E), .FR0F(FR8F), .FR10(FR90), .FR11(FR91), .FR12(FR92), .FR13(FR93), .FR14(FR94), .FR15(FR95), .FR16(FR96), .FR17(FR97), .FR18(FR98), .FR19(FR99), .FR1A(FR9A), .FR1B(FR9B), .FR1C(FR9C), .FR1D(FR9D), .FR1E(FR9E), .FR1F(FR9F), .FR20(FRA0), .FR21(FRA1), .FR22(FRA2), .FR23(FRA3), .FR24(FRA4), .FR25(FRA5), .FR26(FRA6), .FR27(FRA7), .FR28(FRA8), .FR29(FRA9), .FR2A(FRAA), .FR2B(FRAB), .FR2C(FRAC), .FR2D(FRAD), .FR2E(FRAE), .FR2F(FRAF), .FR30(FRB0), .FR31(FRB1), .FR32(FRB2), .FR33(FRB3), .FR34(FRB4), .FR35(FRB5), .FR36(FRB6), .FR37(FRB7), .FR38(FRB8), .FR39(FRB9), .FR3A(FRBA), .FR3B(FRBB), .FR3C(FRBC), .FR3D(FRBD), .FR3E(FRBE), .FR3F(FRBF), // Control Interface .regWA(regWA), // HOST Register Write Address .regWD(regWD), // HOST Register Write Data .regWS(regWS), // HOST Register Write Strobe .regRA(regRA), // Register Read Address .regRD(regRD), // Register Read Data // Global clock and reset .rst(rst), .clk(clk) ); // ====================================================================== // HOST Register Map // ====================================================================== assign TestSel = HR00; assign UART_Control = HR01; //assign = HR02; assign DPRAM_WD[ 7: 0] = HR03; assign DPRAM_WD[15: 8] = HR04; assign DPRAM_WD[23:16] = HR05; assign DPRAM_WD[31:24] = HR06; assign DPRAM_WD[39:32] = HR07; assign DPRAM_WD[47:40] = HR08; assign DPRAM_WD[55:48] = HR09; assign DPRAM_WD[63:56] = HR0A; assign DPRAM_WA[ 7: 0] = HR0B; assign DPRAM_WA[15: 8] = HR0C; //assign DPRAM_RA[ 7: 0] = HR0D; //assign DPRAM_RA[15: 8] = HR0E; assign DPRAM_CTL = HR0F; assign SPI_HOST_Source = HR10; assign SPI_HOST_Packet_TX[ 7: 0] = HR11; assign SPI_HOST_Packet_TX[15: 8] = HR12; assign SPI_HOST_Length = HR13; assign SPI_HOST_ClkDiv = HR14; assign SPI_HOST_Control = HR15; assign SPI_HOST_Target = HR16; assign OE[ 7: 0] = HR17; assign OE[15: 8] = HR18; assign OE[23:16] = HR19; assign O[ 7: 0] = HR1A; assign O[15: 8] = HR1B; assign O[23:16] = HR1C; assign LOOP_CRD[ 7:0] = HR1D; assign LOOP_CRD[15:8] = HR1E; assign LOOP_CR = HR1F; assign SRAM_Control = HR20; assign SRAM_WD = HR21; assign SRAM_Ain[ 7: 0] = HR22; assign SRAM_Ain[15: 8] = HR23; assign SRAM_Ain[23:16] = HR24; //assign = HR25; //assign = HR26; //assign = HR27; //assign = HR28; //assign = HR29; //assign = HR2A; //assign = HR2B; assign PulseEn = HR2C; assign PulseRstB = HR2D; assign SquareEn = HR2E; assign SquareRstB = HR2F; assign PeriodByte0 = HR30; assign PeriodByte1 = HR31; assign PeriodByte2 = HR32; assign PeriodByte3 = HR33; assign PeriodByte4 = HR34; assign PeriodByte5 = HR35; assign PeriodByte6 = HR36; assign PeriodByte7 = HR37; assign PeriodByte8 = HR38; assign PeriodByte9 = HR39; assign PeriodByteA = HR3A; assign PeriodByteB = HR3B; assign PeriodByteC = HR3C; assign PeriodByteD = HR3D; assign PeriodByteE = HR3E; assign PeriodByteF = HR3F; // ====================================================================== // FPGA Register Map // ====================================================================== //assign FR80 = ; //assign FR81 = ; //assign FR82 = ; assign FR83 = DPRAM_RD[ 7: 0]; assign FR84 = DPRAM_RD[15: 8]; assign FR85 = DPRAM_RD[23:16]; assign FR86 = DPRAM_RD[31:24]; assign FR87 = DPRAM_RD[39:32]; assign FR88 = DPRAM_RD[47:40]; assign FR89 = DPRAM_RD[55:48]; assign FR8A = DPRAM_RD[63:56]; //assign FR8B = ; //assign FR8C = ; //assign FR8D = ; //assign FR8E = ; //assign FR8F = ; //assign FR90 = ; assign FR91 = SPI_Packet_RX[ 7: 0]; assign FR92 = SPI_Packet_RX[15: 8]; //assign FR93 = ; //assign FR94 = ; //assign FR95 = ; //assign FR96 = ; //assign FR97 = ; //assign FR98 = ; //assign FR99 = ; assign FR9A = I[ 7: 0]; assign FR9B = I[15: 8]; assign FR9C = I[23:16]; //assign FR9D = ; //assign FR9E = ; //assign FR9F = ; assign FRA0 = SRAM_Status; // FPGA Memory Assignments assign FRA1 = HOST_RB_DataOut[31:24];// Readback Data assign FRA2 = HOST_RB_DataOut[7:0]; // Readback Address LSB assign FRA3 = HOST_RB_DataOut[15:8]; // Readback Address assign FRA4 = HOST_RB_DataOut[23:16];// Readback Address MSB //assign FRA5 = ; //assign FRA6 = ; //assign FRA7 = ; //assign FRA8 = ; //assign FRA9 = ; //assign FRAA = ; //assign FRAB = ; //assign FRAC = ; //assign FRAD = ; //assign FRAE = ; //assign FRAF = ; //assign FRB0 = ; //assign FRB1 = ; //assign FRB2 = ; //assign FRB3 = ; //assign FRB4 = ; //assign FRB5 = ; //assign FRB6 = ; //assign FRB7 = ; //assign FRB8 = ; //assign FRB9 = ; //assign FRBA = ; //assign FRBB = ; //assign FRBC = ; //assign FRBD = ; //assign FRBE = ; //assign FRBF = ; // ====================================================================== // ====================================================================== // Signal to Port Maps // ====================================================================== // This section contains the code that connects internal signals to the // external I/O. It is located at the end of the code so that the all of // the internal signals can be declared where appropriate above. // // If a particular Port pin is not used, it is driven LO. // // ====================================================================== // On-board I/O // ====================================================================== IBUFG D2OSC (.I(D2_OSC), .O(clk)); // Master Clock IBUFG D2BTN (.I(D2_BTN), .O(rst)); // Master Reset OBUF D2LED (.O(D2_LED), .I(LO)); // LED Output // ====================================================================== // RS232 Interface // ====================================================================== IBUF D2TXD (.I(D2_TXD), .O(TXD)); IBUF D2RTS (.I(D2_RTS), .O(RTS)); OBUF D2RXD (.O(D2_RXD), .I(RXD)); OBUF D2CTS (.O(D2_CTS), .I(CTS)); OBUF D2DSR (.O(D2_DSR), .I(DSR)); // ====================================================================== // Port A Interface // ====================================================================== // TOP PINS // PA_01 // Vss // PA_03 // 3.3V IOBUF PA_05 (.IO(PortA[5]), .T(MEM1_WEb), .I(MEM1_WD[0]), .O(MEM1_RD[0])); // MEM1:D0 IOBUF PA_07 (.IO(PortA[7]), .T(MEM1_WEb), .I(MEM1_WD[1]), .O(MEM1_RD[1])); // MEM1:D1 IOBUF PA_09 (.IO(PortA[9]), .T(MEM1_WEb), .I(MEM1_WD[2]), .O(MEM1_RD[2])); // MEM1:D2 IOBUF PA_11 (.IO(PortA[11]),.T(MEM1_WEb), .I(MEM1_WD[3]), .O(MEM1_RD[3])); // MEM1:D3 IOBUF PA_13 (.IO(PortA[13]),.T(MEM1_WEb), .I(MEM1_WD[4]), .O(MEM1_RD[4])); // MEM1:D4 IOBUF PA_15 (.IO(PortA[15]),.T(MEM1_WEb), .I(MEM1_WD[5]), .O(MEM1_RD[5])); // MEM1:D5 IOBUF PA_17 (.IO(PortA[17]),.T(MEM1_WEb), .I(MEM1_WD[6]), .O(MEM1_RD[6])); // MEM1:D6 IOBUF PA_19 (.IO(PortA[19]),.T(MEM1_WEb), .I(MEM1_WD[7]), .O(MEM1_RD[7])); // MEM1:D7 OBUF PA_21 (.O(PortA[21]), .I(LO)); OBUF PA_23 (.O(PortA[23]), .I(MEM1_A[7])); // MEM1:A7 OBUF PA_25 (.O(PortA[25]), .I(MEM1_A[9])); // MEM1:A9 OBUF PA_27 (.O(PortA[27]), .I(MEM1_A[11])); // MEM1:A11 OBUF PA_29 (.O(PortA[29]), .I(MEM1_A[13])); // MEM1:A13 OBUF PA_31 (.O(PortA[31]), .I(MEM1_A[15])); // MEM1:A15 OBUF PA_33 (.O(PortA[33]), .I(MEM1_A[17])); // MEM1:A17 OBUF PA_35 (.O(PortA[35]), .I(MEM1_A[18])); // MEM1:A18 OBUF PA_37 (.O(PortA[37]), .I(LO)); OBUF PA_39 (.O(PortA[39]), .I(LO)); // BOTTOM PINS // PA_02 // Vunreg OBUF PA_04 (.O(PortA[4]), .I(MEM1_A[0])); // MEM1:A0 OBUF PA_06 (.O(PortA[6]), .I(MEM1_A[1])); // MEM1:A1 OBUF PA_08 (.O(PortA[8]), .I(MEM1_A[2])); // MEM1:A2 OBUF PA_10 (.O(PortA[10]), .I(MEM1_A[3])); // MEM1:A3 OBUF PA_12 (.O(PortA[12]), .I(MEM1_A[4])); // MEM1:A4 OBUF PA_14 (.O(PortA[14]), .I(MEM1_A[5])); // MEM1:A5 OBUF PA_16 (.O(PortA[16]), .I(MEM1_WEb)); // MEM1:WEb OBUF PA_18 (.O(PortA[18]), .I(MEM1_OE)); // MEM1:OE OBUF PA_20 (.O(PortA[20]), .I(MEM1_CS[0])); // MEM1:CS0 OBUF PA_22 (.O(PortA[22]), .I(MEM1_CS[1])); // MEM1:CS1 OBUF PA_24 (.O(PortA[24]), .I(MEM1_A[6])); // MEM1:A6 OBUF PA_26 (.O(PortA[26]), .I(MEM1_A[8])); // MEM1:A8 OBUF PA_28 (.O(PortA[28]), .I(MEM1_A[10])); // MEM1:A10 OBUF PA_30 (.O(PortA[30]), .I(MEM1_A[12])); // MEM1:A12 OBUF PA_32 (.O(PortA[32]), .I(MEM1_A[14])); // MEM1:A14 OBUF PA_34 (.O(PortA[34]), .I(MEM1_A[16])); // MEM1:A16 OBUF PA_36 (.O(PortA[36]), .I(LO)); OBUF PA_38 (.O(PortA[38]), .I(LO)); OBUF PA_40 (.O(PortA[40]), .I(LO)); // ====================================================================== // Port B Interface // ====================================================================== // TOP PINS // PB_01 // Vss // PB_03 // 3.3V OBUF PB_05 (.O(PortB[5]), .I(LO)); OBUF PB_07 (.O(PortB[7]), .I(LO)); OBUF PB_09 (.O(PortB[9]), .I(LO)); IBUFG PB_11 (.I(PortB[11]), .O(FRBF[0])); // FPGA: BF = 0x01 (Global Clk) // BOTTOM PINS // PB_02 // Vunreg OBUF PB_04 (.O(PortB[4]), .I(LO)); OBUF PB_06 (.O(PortB[6]), .I(LO)); OBUF PB_08 (.O(PortB[8]), .I(LO)); OBUF PB_10 (.O(PortB[10]), .I(LO)); IBUFG PB_12 (.I(PortB[12]), .O(FRBF[4])); // FPGA: BF = 0x10 (Global Clk) // ====================================================================== // Port C Interface // ====================================================================== // TOP PINS // PC_01 // Vss // PC_03 // 3.3V IOBUF PC_05 (.IO(PortC[5]), .T(OE[0]), .I(O[0]), .O(I[0])); IOBUF PC_07 (.IO(PortC[7]), .T(OE[1]), .I(O[1]), .O(I[1])); IOBUF PC_09 (.IO(PortC[9]), .T(OE[2]), .I(O[2]), .O(I[2])); IOBUF PC_11 (.IO(PortC[11]), .T(OE[3]), .I(O[3]), .O(I[3])); IOBUF PC_13 (.IO(PortC[13]), .T(OE[4]), .I(O[4]), .O(I[4])); IOBUF PC_15 (.IO(PortC[15]), .T(OE[5]), .I(O[5]), .O(I[5])); IOBUF PC_17 (.IO(PortC[17]), .T(OE[6]), .I(O[6]), .O(I[6])); IOBUF PC_19 (.IO(PortC[19]), .T(OE[7]), .I(O[7]), .O(I[7])); IOBUF PC_21 (.IO(PortC[21]), .T(OE[8]), .I(O[8]), .O(I[8])); IOBUF PC_23 (.IO(PortC[23]), .T(OE[9]), .I(O[9]), .O(I[9])); IOBUF PC_25 (.IO(PortC[25]), .T(OE[10]), .I(O[10]), .O(I[10])); IBUF PC_27 (.I(PortC[27]), .O(MISO)); // SPI:MISO OBUF PC_29 (.O(PortC[29]), .I(MOSI)); // SPI:MOSI OBUF PC_31 (.O(PortC[31]), .I(SSN[0])); // SPI:SSN[0] OBUF PC_33 (.O(PortC[33]), .I(SCK)); // SPI:SCK IOBUF PC_35 (.IO(PortC[35]), .T(OE[11]), .I(O[11]), .O(I[11])); IOBUF PC_37 (.IO(PortC[37]), .T(OE[12]), .I(O[12]), .O(I[12])); IOBUF PC_39 (.IO(PortC[39]), .T(OE[13]), .I(O[13]), .O(I[13])); // BOTTOM PINS // PC_02 // Vunreg IOBUF PC_04 (.IO(PortC[4]), .T(OE[14]), .I(O[14]), .O(I[14])); IOBUF PC_06 (.IO(PortC[6]), .T(OE[15]), .I(O[15]), .O(I[15])); OBUF PC_08 (.O(PortC[8]), .I(LO)); OBUF PC_10 (.O(PortC[10]), .I(LO)); OBUF PC_12 (.O(PortC[12]), .I(LO)); OBUF PC_14 (.O(PortC[14]), .I(LO)); OBUF PC_16 (.O(PortC[16]), .I(LO)); OBUF PC_18 (.O(PortC[18]), .I(LO)); OBUF PC_20 (.O(PortC[20]), .I(LO)); OBUF PC_22 (.O(PortC[22]), .I(LO)); OBUF PC_24 (.O(PortC[24]), .I(LO)); OBUF PC_26 (.O(PortC[26]), .I(LO)); OBUF PC_28 (.O(PortC[28]), .I(LO)); OBUF PC_30 (.O(PortC[30]), .I(LO)); OBUF PC_32 (.O(PortC[32]), .I(LO)); OBUF PC_34 (.O(PortC[34]), .I(LO)); OBUF PC_36 (.O(PortC[36]), .I(LO)); OBUF PC_38 (.O(PortC[38]), .I(LO)); OBUF PC_40 (.O(PortC[40]), .I(LO)); // ====================================================================== // Port D Interface // ====================================================================== // TOP PINS // PC_01 // Vss // PC_03 // 3.3V OBUF PD_05 (.O(PortD[5]), .I(Test[0])); OBUF PD_07 (.O(PortD[7]), .I(Test[1])); OBUF PD_09 (.O(PortD[9]), .I(Test[2])); OBUF PD_11 (.O(PortD[11]), .I(Test[3])); OBUF PD_13 (.O(PortD[13]), .I(Test[4])); OBUF PD_15 (.O(PortD[15]), .I(Test[5])); OBUF PD_17 (.O(PortD[17]), .I(Test[6])); OBUF PD_19 (.O(PortD[19]), .I(Test[7])); OBUF PD_21 (.O(PortD[21]), .I(Test[8])); OBUF PD_23 (.O(PortD[23]), .I(Test[9])); OBUF PD_25 (.O(PortD[25]), .I(Test[10])); OBUF PD_27 (.O(PortD[27]), .I(Test[11])); OBUF PD_29 (.O(PortD[29]), .I(Test[12])); OBUF PD_31 (.O(PortD[31]), .I(Test[13])); OBUF PD_33 (.O(PortD[33]), .I(Test[14])); OBUF PD_35 (.O(PortD[35]), .I(Test[15])); OBUF PD_37 (.O(PortD[37]), .I(LO)); OBUF PD_39 (.O(PortD[39]), .I(LO)); // BOTTOM PINS // PD_02 // Vunreg OBUF PD_04 (.O(PortD[4]), .I(LO)); OBUF PD_06 (.O(PortD[6]), .I(LO)); OBUF PD_08 (.O(PortD[8]), .I(LO)); OBUF PD_10 (.O(PortD[10]), .I(LO)); OBUF PD_12 (.O(PortD[12]), .I(LO)); OBUF PD_14 (.O(PortD[14]), .I(LO)); OBUF PD_16 (.O(PortD[16]), .I(LO)); OBUF PD_18 (.O(PortD[18]), .I(LO)); OBUF PD_20 (.O(PortD[20]), .I(LO)); OBUF PD_22 (.O(PortD[22]), .I(LO)); OBUF PD_24 (.O(PortD[24]), .I(LO)); OBUF PD_26 (.O(PortD[26]), .I(LO)); OBUF PD_28 (.O(PortD[28]), .I(LO)); OBUF PD_30 (.O(PortD[30]), .I(LO)); OBUF PD_32 (.O(PortD[32]), .I(LO)); OBUF PD_34 (.O(PortD[34]), .I(LO)); OBUF PD_36 (.O(PortD[36]), .I(LO)); OBUF PD_38 (.O(PortD[38]), .I(LO)); OBUF PD_40 (.O(PortD[40]), .I(LO)); // ====================================================================== endmodule